All modern CPUs must utilize local memory cache to minimize latency of fetching instructions and data from memory.

所有现代的CPU必须使用本地存储的缓存，将获取指令和数据的延迟降到最低。

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Matching work partitions to their data partitions will increase the probability of a cache hit within the server and decrease remote accesses to the database, which introduces quite a bit of latency.

将工作分区与它们的数据分区进行匹配，这将增加服务器缓存的命中概率，并减少对数据库的远程访问，后者会引起较大的延迟。

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Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).

由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。

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