Bus design methodology for the HDTV system-on-a-chip (SoC) decoder is presented. Time sliced arbitration scheme, incorporated with synchronization control of HDTV decoding, is employed in the bus design process.
本文给出了HDTV集成解码芯片的一种总线设计方案。
参考来源 - HDTV集成解码芯片的一种总线设计·2,447,543篇论文数据，部分数据来源于NoteExpress
CAN bus design of inverter is presented.
给出了变频器中CAN总线的设计方案。
Now a new bus design has been unveiled and it has been wowing Londoners.
如今，一款新型双层巴士的设计惊艳亮相，赢得了伦敦人的盛赞。
The reliability of the CAN bus is always an important guide line for the CAN bus design.
CAN总线网络的可靠性历来是CAN总线网络设计时需要考虑的一项重要指标；
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