To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).

为了加快地址转换，架构中有一个 processor-on-a-chip (PoC) 缓存和相关的转换后备缓冲器 (TLB) 逻辑。

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The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.

评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。

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The performance improvement is due to the reduction of Translation Lookaside Buffer (TLB) misses, which occurs because the TLB can now map to a much larger virtual memory range.

性能之所以得到了改进，是因为提高了Translation Lookaside Buffer (TLB)的命中率，这是因为TLB可以映射到更大的虚拟内存范围。

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