All the multiplier architectures proposed in this thesis are bit-parallel finite field multipliers which canimprove the efficiency of cryptosystems significantly.
考虑到目前信息安全系统的有效性,本文所提出的有限域乘法器结构均为位并行乘法器。
参考来源 - 有限域乘法器的设计实现与优化·2,447,543篇论文数据，部分数据来源于NoteExpress
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
SCSI-1 定义了一种具有 5MHz 数据时钟的 8-bit 并行接口，能提供最高 5 兆字节每秒（5 MB/s）的数据传输速率。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
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