The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
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