asynchronous clock domain 异步时钟域
asynchronous clock domains 异步时钟域
multi-asynchronous clock design 多时钟域设计
asynchronous multi-clock system 异步多时钟系统
Above all, this dissertation researched on the synchronizer design of system in asynchronous clock domain from the theory, discussed the solution for some common problem as metastabiliy, race and hazard, empty/full flag generating and etc.
综上所述,本文对异步时钟域的数据同步进行了较深入的研究,讨论了亚稳态,地址毛刺,空/满标志产生等常见问题的解决方案,并以之为理论基础成功实现了项目的设计指标。
参考来源 - 异步多时钟域系统的同步设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
Asynchronous Clock Designs ; Clifford E. Cummings.
非常精典的异步时钟域设计文章。
The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate.
把所述自适应滤波器（15）和减法器（16）与异步时钟（18）耦合以便以异步采样率操作。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
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