bus arbitration logic 总线仲裁逻辑
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.
实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；
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