The SP505 also includes a latch enable pin with the driver and receiver address decoder.

SP505还包括一个带有驱动器和接收器地址译码器的锁存使能管脚。

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We use the CPLD to realize some control circuits, such as address decoder circuits and generate the sample impulses.

这里CPLD主要实现逻辑控制部分的作用，主要完成了采样脉冲产生、地址译码等功能。

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In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.

论文中设计了一种高密度的译码器电路架构，同时针对阵列提出了解决读取和编程时存在的阵列横向导通电流问题。

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