A self-test scheme, under which all test patterns for adder under test in VLSI are produced by the adder self, is presented based on arithmetic additive generator.

基于算术加法测试生成，提出了VLSI中加法器的一种自测试方案：加法器产生自身所需的所有测试矢量。

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A low power test approach for test or built-in self-test based on arithmetic additive generator is proposed in this paper.

本文提出了一种基于算术加法生成器的测试或内建自测试的低功耗测试方法。

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