... 加法器输出缓冲器 adder output buffer，AOB 加法器树 adder tree，AT 加法累积器 adder-accumulator ...
基于14个网页-相关网页
adder tree multiplication 加法器树形乘法
pseudo-adder tree [计] 伪加法树
half adder tree 半加树
adder array tree 加法树
tree adder 树型加法器
Wallace tree adder Wallace树加法器
adder r tree multiplication 加法器树形乘法
prefix tree-like adder 前置树型加法器
The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。
In order to deal with the significant digits addition we designed three inputs adder tree, and give a simple performance discuss of this method.
针对有效数相加问题，本文提出了三输入加法树的设计方法，并就其性能作了简要的分析。
We also describe the principle and possibilities of the all-optical prefix tree adder.
描述了该全光前缀树加法器的原理，说明了其实现的可能性。
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