The structure and design of adder or subtraction of float-point number with single precision are studied under the Active-HDL software environment of the Aldec company. It is designed and simulated with VHDL,and the precision can reach 10-7.
研究了单精度浮点数加/减法的结构及其设计方法,并在A ldec公司的Active-HDL软件环境下,采用VHDL语言进行设计,并进行了仿真验证,计算精度可以达到10-7。
参考来源 - 基于VHDL实现单精度浮点数的加/减法运算·2,447,543篇论文数据，部分数据来源于NoteExpress
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