a-c logical circuit 交流逻辑电路
HDL is an essential general tool in digital logical circuit design. A HDL implementation of the integral bit synchronization with good performance is provided.
HDL是设计数字逻辑电路必不可少的通用工具，该文给出了位同步性能较好的积分型自同步的一个HDL实现。
In other words, the circuit may be physical two - wire (or even physical one - wire) and logical four - wire, performing as a four - wire circuit but employing fewer than four wires.
换句话说，电路可以是物理双线(甚至是物理单线)、逻辑四线，它使用较少的线实现四线电路。
The said digital gate circuit macro model can be used to perform a logical simulation for gate circurit and the digital circuit formed by the gate circuit.
提出了一种建立数字门电路宏模型的方法 ，采用该方法建立的门电路宏模型可以对门电路以及由门电路构成的数字电路进行逻辑仿真 。
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