基于VERILOG的一种高效验证平台的研究及应用 -文本浏览模式- 文档 - 枢研网 关键词:验证平台,自检查,VerilogHDL,结构优化 [gap=564]Keywords:Testbench,Self-check,VerilogHDL,Constructionoptimization
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The verification platform has some useful references for other SoC design.
该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。
参考来源 - 一种双核SoC调试系统的设计与验证Top-down design method by using HDL-verilog is adopted here,function verification of soft IP is completed via constructing testbench as well as extracting function testcases. Perl language scripts programs are also developed in order to improve the efficiency of function verification.
这里采用HDL-Verilog语言进行自顶向下的设计,通过搭建验证平台、提取功能验证点完成软核的功能验证,并且运用Perl开发了脚本程序以提高验证效率。
参考来源 - 通用型I~2C总线的IP设计与验证Automatic verification platform and FPGA prototyping platform are used for the verification of FPGA interface to achieve convergence of verification.
使用自动验证平台与FPGA原型验证平台对FPGA接口进行验证来实现验证的收敛。
参考来源 - 可进化芯片的FPGA接口设计与实现The benefit of using the high verification language to build a verification testbench is of shorter verification cycle, less cost of verification, higher quality of verification.
验证结果表明，采用高级验证语言构建验证平台可有效地缩短验证周期、降低验证成本和提高验证质量。
参考来源 - 交换控制电路功能验证平台设计·2,447,543篇论文数据，部分数据来源于NoteExpress
本文介绍了一种实时视频处理的验证平台。
We introduce a platform for real-time algorithm verification of video processing.
实验模型的建立验证平台的可行性及实用价值。
The experimental model demonstrates the feasibility and practical value of this platform.
实践表明，这种验证平台结构和验证策略，极大地提高了验证的效率和可靠性。
Experimental results show that the platform and strategy greatly improved our verification efficiency and reliability.
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