同时扫描阵列结构也为多时钟域设计以及互连优化提供了方便。

Scan Array can also benefit the design of multiple clock domains and the optimization of connectivity.

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本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。

In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.

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研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。

The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.

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