锁相频率合成器 Phase Locked Frequency Synthesize
锁相环频率合成 PLL syntheized ; PLL Circuit ; PLL frequency synthesis ; PLL
数字锁相频率合成 digital phase-locked frequency synthesizer
数字锁相频率合成器 digital pll frequency synthesizer
相位锁定频率合成 PLL Synthesized
锁相环频率合成器 PLL Frequency Synthesizer ; PLLFS
锁相式频率合成器 [电子] phase-lock frequency synthesizer
锁相环频率合成技术 PLL ; Phase-locked Loop Synthesis ; Phase Lock LoopFrequencySynthesis
锁相回路频率合成器 PLL frequency synthesizer
This paper based on control theory, according to the conception of Phrase Lock Loop and Direct Digital Synthesis, we designed the clock circuit. It realizes the amalgamation of kinds of the ways about clock, which make it has some superiority.
本论文在控制理论的基础上，以锁相频率合成和直接数字频率合成作为设计思想，搭建时钟控制电路，在业界实现了多种时钟控制电路实现方法的融合与统一，具有一定的优越性和领先性。
参考来源 - 综合业务接口板时钟控制电路的设计与实现·2,447,543篇论文数据，部分数据来源于NoteExpress
介绍分频锁相频率合成技术。
The technology of frequency division phase-locked frequency synthesis is introduced.
中频部分主要由HFA3724正交调制解调器和基于MB1502的锁相频率合成电路等组成。
The intermediate frequency circuit includes QPSK modulation based on HFA3724, PLL circuit based on MB1502.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
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