介绍了在地下漏水探测仪中用CPLD实现高速音频数据采集控制及与单片机的接口逻辑设计。
The gathering and controlling of high speed data of audio frequency by CPLD and the logic design of interface are introduced for underground water leakage detecting instrument.
他由一个8位6502 CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
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