介绍了根据工艺要求系统地构成状态表和程序图，写逻辑表达式。画控制线路的具体方法。
It can be used to systematically construct state array and sequence diagram, write logic expressions, and draw control circuit diagram based on technical requirements.
及对时序电路逻辑功能的两种检测技术：基于状态表的测试技术和自动检测技术。
Two test technologies state stable based technology and automatic test technology are given for the test of logic functions of sequential circuit.
由于该时序逻辑综合新方法在处理过程中要涉及解大型覆盖表的问题，为此提出满足压缩状态表约束关系的状态分配的简化算法。
This method, based on combinational logic minimization, proposes a new idea to proceed state assignment according to constrained. relation of compressed state table.
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