采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
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