从理论上说，您可以延迟设计决策到最后责任时刻。

Ideally, you want to defer design decisions to the last responsible moment.

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在等待设计项目的其他部分与主干同步时，常常出现延迟。

Often delays occur while waiting for other parts of the design project to synchronize with the main branch.

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由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。

Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).

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