在计数阶段的最后，主控门关闭，然后计数器复位，开始下一个采样阶段。
At the end of the counting period, the main gate is closed and counter reset for the next sampling period.
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究，提出一种带复位功能的低功耗十进制计数器设计方案。
Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed.
原始条件：使用D触发器（ 74 LS 74 ）、“与”门 （ 74 LS 08 ）、“或”门（ 74 LS 32 ）、非门 （ 74 LS 04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
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