不同偏置电压的输入缓冲晶体管。

Different bias voltage for the input buffer transistor.

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此外，缓冲层可以减少晶体管之间的设备和硅衬底平行的传导问题。

In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate.

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此外，缓冲层地址和缓解晶格薄膜之间的不匹配而相对形成晶体管和硅衬底上。

In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

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