提出了一种全新的电荷泵锁相环的行为级建模方法。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文研究了电荷泵锁相环电路的模型和电路设计。
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
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