用复杂可编程芯片(CPLD)实现，并用于雷达数字光纤通信系统的信道编码，提高了时钟提取的性能。
The scheme can be implemented by using the CPLD chip, and used for the channel coder in a radar digital optic-fiber communication system and improving the features of clock extraction.
大规模集成电路晶元是中等到大规模的记忆晶元，用于8位处理器、数字时钟和计算器。
Lsi chips are medium to large size memory chips, 8 bit microprocessors, digital clocks or calculators.
文中设计的FIR可变分数延迟滤波器用于解决全数字接收机的时钟同步问题。
In this paper, the FIR variable fractional delay filter is designed and used to solve the problem of symbol synchronization of all digital receiver.
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