由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。

Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.

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时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。

Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.

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这将使NVIDIA的提高，最高的时钟频率的内存，从目前的1800兆赫到2200兆赫。

This will allow NVIDIA to raise the maximum clock frequency of memory from present 1800 MHz to 2200 MHz.

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