在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。

To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.

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逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。

Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.

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