该比较器包含一级预放大器、动态锁存器及时钟控制反相器。

The comparator includes a preamplifier, a dynamic latch and a clocked inverter.

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每个看门狗具有一个可选择的预分频器(从1到64 K)，可用于时钟看门狗定时器也能触发dma请求和捕获比较通道。

Each watchdog has a selectable prescaler (from 1 to 64 k) that can be used to clock the watchdog timers which can also trigger DMA requests and capture compare channels.

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在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。

For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.

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