利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
选用复杂可编程器件(CPLD)作为硬件设计载体，使用VHDL语言对驱动时序发生器进行了硬件描述。
Complex program logic device (CPLD) has been chosen as the hardware design platform, driving schedule generator has been described with VHDL.
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