数字逻辑系统的设计离不开计算机辅助设计CAD工具的帮助,尤其是VHDL硬件描述语言。
Now, many digital logic systems cannot do without computer aided design CAD, especially the VHDL Hardware Description Language.
结合工程实践和大量应用文献总结出高速数字逻辑系统的设计方法,以及高速数字系统的性能测试方法。
Furthermore, the design rules of high-speed digital systems and their self-checking and testing techniques are summed up by combining the project experience and lots of application literature.
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