目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
There are some common methods of design for testability, such as boundary scan test and so on.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
提出了一种在内建自测试(BIST)中进行部分扫描的算法，此算法综合了电路的结构分析和可测性分析。
A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.
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