支持外部等待时钟信号延长总线周期。

Supports external wait signal to expend the buS cycle.

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采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。

The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.

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总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。

The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.

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