However, Time-interleaved parallel sampling technique relies on the exact matching of channels.
然而,TIADC并行采样技术依赖于各通道间参数的精确匹配。
参考来源 - 高速TIADC并行采样系统综合校正技术研究·2,447,543篇论文数据，部分数据来源于NoteExpress
本系统主要由函数产生模块、并行采样模块和线性运算模块组成。
The system is mainly composed of a function generating module, a parallel sampling module and a linear operating module.
当输入信号的频率足够高时，一般采用并行处理技术或等效采样技术。
When the frequency of the input signal is high enough, parallel processing or equivalent sampling is used.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
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