Ps22Pdf 关键词 : 并行乘法器 ; Booth2; Wallace 树 [gap=770]Key words: Parallel Multiplier; Booth2; Wallace Tree
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... one-shot exploder 单发起爆器 one-shot multiplier 并行乘法器 ; 串并行乘法器 one-hand shot 单手射门 ...
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串／并行乘法器 serialperallel multiplier
半并行乘法器 Semi-parallel multiplication
串-并行乘法器 one-shot multiplier
串并行乘法器 one-shot multiplier
可伸缩分组并行乘法器 Digit-serial multiplier
The implementation and simulation of a 6-bit parallel multiplier is presented to demonstrate that the new reconfigurable array can reduce the time complexity of fault-tolerance and improve the utilization rate of the redundancy resources.
以6×6并行乘法器为例,验证了新型可重构阵列能够降低容错时间复杂度并提高冗余资源利用率。
参考来源 - 可重构硬件内建自测试与容错机制研究·2,447,543篇论文数据，部分数据来源于NoteExpress
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
根据平行并行乘法器，设计了适用于模乘运算的一维阵列组合乘法器。
The one-array combinative multiplication was designed on the basis of the parallel multiplication.
在此基础上，借助于对比特级并行乘法器的复杂度的分析，给出了一个优化最大距离可分码的算法。
Based on these, an algorithm to optimize MDS codes is introduced by analyzing the complexity of bit parallel multipliers.
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