基于CPLD的正交脉冲小数分频技术-计算机与信息技术论文-论文中国 关键字：正交脉冲；复杂可编程逻辑元件；小数分频；伺服系统 [gap=649]Keyword: orthogonal pulse;CPLD;fractional frequency division;servo system
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Its output clock frequency can be very high due to the high frequency capacity of the VCO in the fractional-N PLL. The all-digital PLL has been implemented in UMC 0.13um process.
而此全数字锁相环的输出时钟是由小数分频锁相环中的压控振荡器直接产生,其频率上限在目前0.13微米的工艺中,可以达到几吉赫兹,完全可以满足绝大多数的应用需要。
参考来源 - 高速低抖动全数字锁相环的设计研究·2,447,543篇论文数据，部分数据来源于NoteExpress
文中介绍了一种小数分频频率合成器的设计方案。
In this paper, a solution to fractional frequency dividing frequency synthesizer is introduced.
该合成器采用程控时分复用小数分频锁相技术，解决了快速跳频频率合成中的诸多固难。
Some technique problems in fast frequency hopping synthesis are solved by making use of a programmable time division-fractional division PLL.
文中介绍了小数分频技术的基本原理，并分析了小数分频中小数杂散产生原因和抑制方法。
This paper introduces the basic principles of fractional technology, and analyzes the cause of fractional spurious and the method of suppression.
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