设计实现了一种改进的高扇入多米诺电路结构。
模拟结果表明，设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗，减小了总的漏电流，同时提高了工作速度。
The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions.
介绍一种全部由PMOS休眠管实现的双阈值电压多米诺逻辑电路。
One new domino logic circuit whose architecture is based on full PMOS sleep transistors and a dual threshold voltage CMOS technology is introduced.
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