相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。

A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.

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当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。

When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.

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环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。

The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

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