本文提出一种异步时序电路设计的符号卡诺图的新方法。

This paper presents a new method of asynchronous design is illustrated by the symbolic Karnaugh map.

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文章介绍了在数字逻辑电路设计中降维卡诺图的建立和应用。

This paper discusses the foundation and the application of reduced-dimension Karnaugh map in numeral logical circuit design.

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对数字电路中卡诺图化简、时序电路分析和集成电路教学等三个问题的教学方法进行一定的分析和探讨。

This paper is a discussion on some teaching methods of the simplification for Karnaugh map, the analysis of sequential circuit and the teaching of integrated circuits.

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