背板上的总线时钟和数据线的分布，互连设计显得尤为重要。
Especially in the bus design on the backplane, we should pay more attention to the distribution, interconnection of the clock, data line.
安装简单的紧凑型设计为军事，工业，商业应用的互连设计提供了新的考验。
The installation of a simple compact design provides a new test for the interconnection of military, industrial, and commercial applications.
本文介绍了高速并行总线互连设计中出现的信号完整性问题及新的设计方法学。
This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology.
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