固定的棕榈树砍锁相互作用和菜单。
所用的电路为蔡氏电路和锁相环电路。
数字锁相环是数字解调器的关键部件。
Digital phase lock loop is a key part of the digital demodulator.
锁相放大是微弱信号检测的重要手段。
Lock-in amplifying (LIA) is one of important means for weak signal detection.
锁相环在很多领域都得到了广泛应用。
它没有首先测试那些真正与锁相关的场景！
It omits testing the very situation that makes locking relevant in the first place!
这些与锁相关的控制都是数据库配置参数。
These lock-related controls are database configuration parameters.
锁相环电路，相移方法，及集成电路芯片。
Phase-locking loop circuit, phase shifting method, and IC chip.
介绍了高稳定锁相调制和高灵敏度的接收解调。
High stability PLL-modulator and high sensitivity receiving demodulator are introduced.
利用锁相环路原理提出锁相自动准同期控制方案。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
锁相式频率合成技术提供了解决这一问题的思路。
Phase locked loop technique offers a way to resolve this problem.
特别地，锁相热成像更适合用来检测复合材料结构。
In particular, Lock - in thermography is more suitable to detect composite material structure.
提出了一种具有自动变模控制的快速全数字锁相环。
A fast all digital phase-locked loop with automatic modulus control is presented.
锁相接收机的作用是重建原信号而尽可能地去除噪声。
The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.
在本文中，我们将展现一个新的锁相环锁定检测方法。
In this paper, a new method of PLL lock detector will be presented.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
数字锁相环路（DPLL）是数字相干解调技术的核心。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
在通信领域中，锁相环频率合成器起着越来越重要的角色。
In the field of communications, PLL synthesizers playing an increasingly important role.
将制作的锁相放大器应用在了利用声波的相位差定位的系统中。
Then the LIA is used in a system which finds out the location of a sound source.
本文介绍软件锁相的特点、设计技巧及其在电工测量仪表中的应用。
This paper introduces software phase locking, its features, design skill, and application in electrotechnical measuring instrument.
小组发现锁相和不稳定重新同步周期的持续时间都遵守幂次定律分布。
The team found that the duration both of phase-locking and unstable resynchronisation periods followed a power-law distribution.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
该锁相环由计算频率误差、更新环路中间变量、输出控制信号组成。
The SPLL consists of calculation frequency error, updating loop middle variable, and output control signal.
本文提出一种利用低频锁相放大器测量高频信号的混频-锁相检测技术。
The mix-lookin detection technique for high frequency signal measurement with low frequency look-in amplifier is presented.
大脑里锁相和不稳定之间的平衡也被关联到智力-至少和IQ测试的成绩有关。
The balance between stability and instability in the brain has been linked with intelligence, at least as measured by scores on an IQ test
在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.
为了抑制噪声的影响，应用交流技术开发了有更高精度的锁相微分电导测量系统。
In order to depress the noise, a lock-in differential conductance measurement system is designed.
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
他发现儿童大脑停留在稳定锁相状态和不稳定相移状态下的时间和他们的IQ成绩有关。
He found that the length of time the children's brains spent in both the stable phase-locked states and the unstable phase-shifting states correlated with their IQ scores.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
应用推荐