深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
本文讨论了影响互连线延迟的因素，并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。
The factors that affect the interconnect wire delay and the resolution ways from to lower the signal swing and change switch threshold value aspect are described in this paper.
本论文着重论述未来CMOS进入纳米尺寸的关键挑战，如：电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。
Key challenges on CMOS scaling down into nanometer regime are discussed, such as power supply and threshold voltage, short-channel effect, quantum effect, random doping distribution and wire delay.
最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed.
最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed.
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