位散列结果被表示为32个十六进位数字组成的字符串。
The 128-bit hash result is represented as a string of 32 hex digits.
如果得到的和太大以至于用32位装不下它，会产生一个进位。
This might lead to a carry if the sum is too big to fit into 32 bits.
这个进位将包含在高32位的相加中。
This carry is included in the addition of the higher 32 bits.
提出了一种改进进位运算的32位稀疏树加法器。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
注释：个别项目的字是该的平均，进位至最接近的百位。由于四。
Notes : Figures for individual items are yearly averages rounded to the nearest hundreds.
在二进位系统中，信息的每一位不是开就是关，不是一就是零，小是真就是假。
In a binary system, each bit of information is either on or off, one or zero, true or false.
把源值定义的某位复制给进位标志？哪一位？
The destination bit indexed by the source value is copied into the Carry Flag.
二进制编码的十进制数进行相加所需的从第3位到第4位的进位。
The carry from bit3 to bit4 needed for adding packed binary coded decimal number correctly, where two binary coded decimal digits reside in one8-bit byte.
当两个多位数相加时，每一位的进位应与高一位数相加。
In the addition of two multibit numbers, the carry of each single bit addition is added to the next-insignificance bit.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
输出信号频率通常可按十进位数字选择，最高能达11位数字的极高分辨力。
Output signal frequency can usually choose to decimal Numbers, to a maximum of 11-digit high resolution.
使所述四进位输出符号的位反相将产生具有(G,i)约束的输出比特流，如在反向串连调制系统中所使用的PRML (G, i)码中那样。
Inverting the bits of the 4-ary output symbols produces an output bit-stream with (g, I) -constraints as in the PRML (g, I) codes used in reverse-concatenation modulation systems.
然后交错每个连续四进位输出符号的位，从而产生具有全局且交错的连串长度约束的输出比特流。
The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints.
在一位数加多位数不进位加法口算中，口算时间差异主要源于运算时间差异和整合时间差异；
In the non-carry mental addition of 1-digit number and multi-digit number, mental arithmetic time differences lie in arithmetic time differences and integration time differences.
在一位数加多位数不进位加法口算中，口算时间差异主要源于运算时间差异和整合时间差异；
In the non-carry mental addition of 1-digit number and multi-digit number, mental arithmetic time differences lie in arithmetic time differences and integration time differences.
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