误码仪是评估信道性能的基本测量仪器。
Error code instrument is a basic test instrument to estimate channel performances.
传统的误码仪在误码率测试时有很多缺陷。
Traditional error code rate testing instrument has many limitations.
本设计研究了传统误码仪的工作原理与结构，并利用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能。
This paper researched the work theory and structure of traditional BERT, and used VHDL program language to realize a majority of BERT functions on FPGA.
简述了FPGA在高速位误码率测试仪中的应用，对误码率测试仪的结构，及其FPGA实现进行了详细的介绍。
The structure of the high-speed BER testing instrument is introduced. The application of FPGA in the instrument and the realization of FPGA are expounded.
第三章介绍高速误码率测试仪发端子系统的设计方案；
The third chapter discusses transmitter' s de-sign scheme of high speed BERT.
文中给出了PMC4351在2M误码测试仪中的工作原理及应用电路，论述了2 M误码测试仪系统软件，并给出了PMC4351的初始化程序。
This paper introduces its operation principle and application circuit in 2m measure instrument, and provides the software of 2m measure instrument system and initiation programme of PMC4351.
设计出一款体积小、重量轻、成本低、性能稳定的低速率误码测试仪。
It has advantages of small volume, light weight, high efficiency, wide voltage stabilizing range, no waveform distorion etc.
设计出一款体积小、重量轻、成本低、性能稳定的低速率误码测试仪。
It has advantages of small volume, light weight, high efficiency, wide voltage stabilizing range, no waveform distorion etc.
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