如何使一个简单的编码器和译码器吗？
提出了一种新颖的MAP译码器结构。
In this paper, a new architecture of MAP decoder is presented.
介绍了一种乘积码迭代译码器的硬件设计方案。
This paper introduces a hardware design of two dimensional product code iterative decoder.
标准时间译码器是有源电视时频同步的专用设备。
The standard time decoder is a special equipment for active TV synchronization.
R S码硬件译码器也可应用于地面接收系统中。
RS hardware decoder can be used in the ground receiver system.
XML是标准语言，很容易为它编写编码器和译码器。
XML is a standard language, and it is very easy to write encoders and decoders for.
介绍了我们研制的交错码的编译码器电路及实验结果。
Circuitry of interlaced encoder and decoder and some experimental results are then given.
说明：利用两个8线译码器做成的一个十六线译码器。
Using a sixteen line decoder and made two of 8 line decoder.
尽管图中没有显示，但指令译码器还有下列功能的控制线。
Although they are not shown in this diagram, there would be control lines from the instruction decoder.
本文提出了一种源于汉明类多层前向神经网络分组码译码器。
This paper presents a neural network decoder of linear block codes which originates from Hamming network.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
译码器测试系统的设计和译码器性能测试是本课题另外两个重要环节。
Other two important tasks of our research project include the design of the verification system and the performance test for the decoder.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
几乎所有的视频编译码器都采用有损压缩，最小化与视频相关的数据量。
Almost all video codecs use lossy compression to minimize the huge amounts of data associated with video.
SP505还包括一个带有驱动器和接收器地址译码器的锁存使能管脚。
The SP505 also includes a latch enable pin with the driver and receiver address decoder.
七段显示译码器是数字电路中的重要部件，其设计多年来采用传统方法。
The Seven-Segment Decoders are important elements of digital circuits. Designing it has used traditional method for many years.
结果表明该方案切实可行，编译码器运行稳定可靠，已用于实际项目中。
Results show this scheme is feasible, the codec runs stable and has been used in practice.
利用多级离子注入技术，一种新型的CMOS四值译码器与编码器被设计。
By using the multiple ion implantation technique, novel CMOS quaternary decoder and encoder are designed.
在论文中，详细介绍了编译码器的整体方案、硬件电路和软件功能的设计。
The scheme of the apparatus, the electro circuit design, and the software design is introduced in the dissertation subsequently.
文章研究多用户MIMO下行链路中线性预编码器和译码器的联合优化问题。
This paper deals with the joint optimization of linear precoders and decoders for multiuser MIMO downlinks.
紧接着讨论了LDPC译码器中的核心运算单元一校验功能单元的硬件设计。
Then it mainly discusses the hardware design of the key unit in LDPC decoder-check functional unit.
本文是关于采用三个TTLD触发器和六个译码器来组成扭形计数器的设计。
This paper is concerned with three TTL D flip-flops and six Decoders which are buith by Ring counter design.
这些通常根据由手动操作的扫描杆连接的超声波探针和译码器确定的位置来绘制。
These often rely on the ultrasonic probe being connected to a manually operated scanning arm with the position being encoded.
该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
该文根据准循环ldpc码的结构特点，提出了一种同步部分并行结构的译码器。
Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper.
在维特比译码器译码时，应用信道状态信息(CSI)，可以明显提高系统性能。
The performance can be improved greatly by using the channel state information (CSI) in Viterbi decoder.
PackageKit寻找合适的编码器和译码器，如果你同意，就会自动被安装。
PackageKit then looks for the appropriate codec and, if you approve, installs it.
控制单元由程序存储器ROM、指令译码器、地址生成模块、程序计算器PC 组成。
The control path contain Instructor ROM, instructor register, instructor decode unit, address creating module and Program Counter (PC)module.
首先采用译码器对输入和输出电压进行判比，确定最优的转换系数，提高了系统的效率。
The decoder determines the optimum conversion ratio to improve the efficiency of system from the relation between the input and output voltage.
首先采用译码器对输入和输出电压进行判比，确定最优的转换系数，提高了系统的效率。
The decoder determines the optimum conversion ratio to improve the efficiency of system from the relation between the input and output voltage.
应用推荐