最后，简化了电路结构，拥有比较小的芯片面积。
At last, the circuit structure has been simplify to make the chip have smaller dimension.
这样，即使采用全扫描设计，也仅需较小的芯片面积。
Thus, only a very small extra chip area is required even if full scan design is used.
同时动态电路在速度、芯片面积等方面也比静态电路有优势。
Meanwhile , it has the advantages in speed and chip integration .
高Q值的开关电容带通双二次节需要很高的电容比和较大的芯片面积。
The realization of high-Q switched-capacitor (SC) bandpass biquadratic- joints require very high capacitor spread and larger chip area.
该方法由于没有采用存储器存储测试模板，所以可以节省一定的芯片面积。
Because this method doesn't use memory to store the test patterns, it can save certain area of the chip.
该芯片具有实现电路简单、输出电压精度高、功耗低、芯片面积小等优点。
The PFM controller of DC-DC converter has the advantages of high precision, simple architecture, low power consumption and small IC footprint.
根据控制逻辑来实施相位选择单元使得能够获得更高的速度并节省芯片面积。
The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.
这也意味着AT I公司花费了大量的芯片面积实施的事情永远不会被使用。
It also meant that ATI spent a lot of silicon area implementing things that would never be used.
选用微带线和衬底接地的共面波导等不同结构的电感实现形式，充分利用了芯片面积。
In this chip, inductors are realized with microstrips or grounded coplanar waveguides according to their actual position, so the chip's area is reduced.
比同档次设计具有更小的芯片面积、更低的功耗和更短的锁定时间，达到了较高的性能指标。
With the comparison of the equivalent design, the proposed HFCG has lower power consumption, faster lock-in time and a smaller die area.
本发明能在不增加任何芯片面积的前提下，有效的定位缺陷存储器，方便缺陷分析和设计改进。
The invention can effectively position a defect memorizer without increasing the chip area, and is convenient for defect analysis and design improvement.
实验结果证明，该改进的算法无论在速度上还是在芯片面积上都具有比以往的算法更优秀的性能。
The result indicates that this optimized algorithm has advanced performance in both speed and area than other past algorithms.
使用的标准单元类型具有较大程度的相似性，有利于基于标准单元布局布线软件进一步减少芯片面积。
Cells used in the circuit have much similarity, which helps further reduction of chip areas in the layout procedure based on standard cells.
提供了一种能够获得对于水平噪声校正有效的校正值并同时抑制摄像装置的芯片面积增大的摄像设备。
An image pickup apparatus is provided that is capable of obtaining a correction value effective for horizontal noise correction, while suppressing increase in chip area of an image pickup device.
所以CORDIC算法来实现软件无线电直接数字频率合成器有助于节省芯片面积、降低功耗、减少成本。
Thus, software radio DDFS based on CORDIC algorithm can help to reduce chip area, power dissipation and cost.
另外，系统的设计采用了异步时序，故减少了芯片的金属连线，减小了芯片面积，降低了产品的生产成本。
Besides, the metal wires and area of the slug are reduced and the production costs are also cut down by using asynchronous sequential circuit.
在放置器件时考虑可能出现的拴锁、匹配和寄生，使其之间的连线最短、交叉最少，并对芯片面积进行了估算。
Latchup, matching and parasitic are considered to make sure the connection lines shortest and the cross points least, finally the chip area is estimated.
设计采用的新型心动阵列结构，可以在有效控制芯片面积的前提下，极大地提高运算频率，从而提高运算速度。
It adopts a new systolic array architecture, which can improve the speed by increasing the frequency without the size increased.
提出了一种实现RSA算法的新型ASIC结构，具有较小的芯片面积和较强的灵活性，适合于智能IC卡应用。
A new ASIC implementation of RSA algorithm is presented. It has less area and more flexibility, making the chip very suitable for smart card applications.
这些存储单元不论是在芯片面积还是功耗上都占有非常大的比重，所以它们的性能决定了整个嵌入式系统的性能。
These memory possess the great proportion of the whole chipset both in the energy consumption and in the chipset area, so the chipset performance is decided by these memory performance.
第一种实现方法的特点是针对F LEX系列器件结构在查找表结构的基础上，对工作速度和占芯片面积进行优化。
The characters of method one is that on the basis of looking table structure in the FLEX series devices, speed and chip area are optimized.
设计中选择了两优先级轮转仲裁算法，以提高系统性能；优化了状态机编码方式，以减小芯片面积和降低动态功耗。
In this design, a 2-level round-robin arbitration algorithm is chosen to improve system performance, and state machine coding style is also optimized to reduce chip size and dynamic power consumption.
折叠内插结构模数转换器由于在速度、分辨率、功耗和芯片面积等方面具有良好的特性而成为了近年来的一个研究热点。
With the nice features in speed, resolution, power consumption and proportion, folding and interpolating analog-digital converter becomes a study hotspot in recent years.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
随着电源电压的不断降低和芯片面积的不断减小，电荷泵的效率已成为MOS电荷泵电路设计过程中最为人们关心的问题之一。
The power efficiency of MOS charge pumping circuit is becoming one of the most important issues as the power supply decreasing continuously and the area of a chip.
PC I AD总线再复用模型不仅可以保证功能正确，而且节约了32根管脚资源，进而缩小了芯片面积，降低了设计成本。
While working normal, the model can decrease 32 pins that decrease the area of the chip, and decrease the design cost.
实验结果表明，在考虑热约束的布局结果中，芯片上各点的温度分布均匀，最热点的温度显著降低，而芯片面积的增加却很少。
The experimental results show that the thermal distributed evenly and the temperature of the "hot spots" decreased greatly in the chip.
该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。
A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.
随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。
An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.
随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。
An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.
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