采用了硬件锁相环技术，可更加有效实现同步采样，提高了采样精度。
Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy.
利用软件实现的锁相环比硬件锁相环具有更好的灵活性和通用性，同时具有结构简单、参数设计灵活等优点。
The PLL designed by software has a higher flexibility and versatility than that by hardware, at the same time it has the advantages of simple in structure and flexible design parameters and etc.
给出了系统总体结构、模拟通道设计、倍频锁相电路、数据采集电路、各种电参数测量算法及系统软硬件抗干扰措施。
The system hardware structure, analog channels circuits, data acquisition circuits, measurement algorithms of electric parameters and anti-jamming methods are given.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
本文提出了一种无需整周期采样、无需锁相环和复杂电路硬件的相位检测算法。
A novel phase detection algorithm that does not need complete period sampling, phase-locked loops or complex electrocircuit hardware was presented in this paper.
为满足高速和精确的采样，论文在控制器硬件中设计了锁相环电路。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
通过对锁相环硬件电路的调试和编写相关单片机控制程序，实现了一个性能较好的频率源。
Through debugging the hardware circuit of the Phase Locked Loop and writing the Single-Chip Processor program, a good performance frequency source is realized.
论文介绍了锁相环原理以及锁相环各组成模块的线性化模型，并进行了软、硬件设计。
Paper describes the principle of the PLL, the linearized model of its modules, its hardware and software implementation.
论文介绍了锁相环原理以及锁相环各组成模块的线性化模型，并进行了软、硬件设计。
Paper describes the principle of the PLL, the linearized model of its modules, its hardware and software implementation.
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