介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
而集成电路的后端设计包括了版图设计和验证，它们不在本论文的讨论范围之内。
The back-end design includes layout design and verification, but they will not be discussed in this paper.
提出了一种有效的验证集成电路版图的网络比较算法。
An efficient network comparison algorithm for layout verification of integrated circuits is presented.
课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules, and makes a lot of SPICE simulation and verification.
生成器配合集成电路后端设计开发环境，可以对所生成的测试结构版图文件进行检查与验证。
With the help of IC back-end tools, this generator could implement the checking and verifying of the generated test structures layout files.
实际操作过程中的检查与验证表明，此生成器可以快速有效地自动生成正确的测试结构版图文件。
The operation of checking and verifying work shows that this generator can generate the test structures layout files automatically, efficiently and accurately.
最后，深入讨论模拟部分版图设计相关问题，并完成了版图设计和验证工作。
Finally, the problems about layout design in analog part are discussed, and layout design and verification are accomplished.
在版图设计上采用自动布局布线，并通过DRC、LVS等验证。
For Layout design, auto place and routing is used and succeeded in DRC, LVS.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
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