最后,文章还对伪流水线型时间数字转换器各级子时间数字转换器进行了优化。
Finally, the paper illustrates the detailed structure of the sub-time-to-digital converter in each stage.
作为全数字锁相环的关键模块,时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
作为全数字锁相环的关键模块,时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
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