在此基础上，得到了求完全定义时序机状态化简的算法。
On this basis, an algorithm for state minimization of completely specified sequential machine is obtained.
同步时序机状态加全模拟是同步时序机反设计的关键步骤。
Full state simulation is a key step in the reverse DE - sign of synchronization sequential machine.
本文提出不完全指定的时序机状态化简的一种计算机算法。
An algorithm for minimizing the number of states in an Incompletely Specified Sequential Machine (ISSM) is put forword.
同步时序机的状态驱动可根据状态图来完成，状态图通常由次态方程求得。
The state drive of a synchronous sequential machine may be finished according to the state diagram which is usually derived from the next state equation.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
IEC 61850对于具有严格时序要求的控制类操作采用“状态机”来定义其通讯服务。
In IEC 61850 the communication services of the controlling operations with strict sequence requirement were defined by state machines.
结果显示，把最小二乘支持向量机回归预测与等步长时序预测相结合的预测方法应用于地下工程围岩位移监测数据的分析及预测是可行的；
Combining the advantages of regression analysis methods and time series forecast model with equal step length, a compound forecasting model was set up , and was tested with engineering data.
给出了PCI总线配置空间的设计以及PCI接口控制器中时序状态机的实现。
The design of the PCI bus in the interspaced ordonnance, and the realization of the sequence state machine in the PCI interface controller is given.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
旋转式吹瓶机的制造效率与稳定性须仰赖正确的时序控制。
The coordination and stability among mechanisms of rotary type blow-molding machines are determined by the correct time sequence.
仲裁与控制模块是顶模块的主体部分，主要实现系统状态机和时序控制；
Arbitration and control module is the main part of the top module used to implement the state machine and system timing control.
整个调制解调器采用FPGA进行时序控制，采用DSP对CMB909进行编程控制、数据帧的打包以及和PC机的串口通信。
Modems used for the entire time series FPGA control, the use of DSP to CMB909 executable program control, data and images of the packaging and communications between PC machine and serial interface.
介绍了一种用单片机控制的微秒级多路时序信号发生器的实现方法。
A new method of microsecond timing generator controlled by microprocessor is introduced in this article.
由主机对从机的绝对访问权限，可灵活实现抢答否决控制，能够按时序区分作弊抢答行为以保证抢答过程中的公平性。
From the host machine from the absolute access, flexibility to achieve Responder veto control, timing can differentiate by cheating Responder Responder act to ensure the fairness of the process.
将单片机应用于电离层探测雷达中，软化了雷达编码器的时序。
The SCM applied in ionospheric sounding radar makes the timing of coder in the radar programmable.
而平面旋转阀的时序又是低温制冷机的一个重要参数，它决定了制冷机系统进气、排气过程之间的相互关系。
The timing of the rotary valve, which is a key operating parameter for cryocoolers, determines the relationship between the intake and exhaust process.
辅以单片机统一系统时序，完成红外视频采集、图像增强和视频输出的功能。
This system will implement the function of infrared video collection, image buildup and video output.
任务调度问题是指根据一定的调度策略，把一组并行处理的任务按规定的时序分配到系统的多个处理机节点上，以期获得较好的系统执行性能。
Task scheduling aims at scheduling a set of partially ordered computational tasks onto a multiprocessor system by a given strategy in order to obtain a better system performance.
在充分了解FPGA的PS配置模式时序的基础上，用单片机at89c 51模拟实现PS配置时序，从而实现FPGA电路重构技术。
According to fully understanding PS configuration timing, AT89C51 simulates and realizes PS configuration timing, and the system realizes the technology of FPGA circuit reconfiguration.
介绍了一种基于FPGA设计的数字化扩频接收机，阐述了接收机各功能模块功能、编程方式及时序关系。
The paper introduces a kind of digital spread spectrum receiver based on FPGA , describes function models, programmable method and time relation.
提出了一种协同攻击机间互联数据链（IDL）的设计方法，对机间数据链的传输方式、传输周期、传输内容、传输时序等进行了研究。
This paper puts forward a design method of IDL for coordinated attack. The IDL's mode, period, content, and order of communication are discussed in this paper.
介绍了线阵CCD传感特性和CCD驱动时序；设计了一种新颖的基于嵌入式单片机的线阵CCD驱动电路、CCD输出模拟信号采集为一体的溶液质量分数检测系统。
A novel linear CCD drive circuit based on embeded MCU is proposed, and liquid quality fraction detection system is elaborated, which is composed of CCD analog output signal acquisition.
给出了一种基于FPGA实现PCI总线目标模块接口控制器的设计方案，用时序状态机来实现总线访问操作复杂的时序。
PCI target interface controller design with FPGA is proposed. And the realization of the complication of the access sequence to the BUS interface controller is expressed by sequence state machine.
接收机对信号进行载波恢复并解调，通过时序恢复后进行解码。
In the receiver, the received signal is demodulated after carrier recovery. And the demodulated signal is decoded after timing recovery.
本文分析了高帧频摄像机数字口输出工作时序，针对其数据量大的特点，提出利用FPGA外部扩展SDRAM的方式存储缓冲图像数据的解决方案。
The camera operation timing is analyzed in this paper. For the feature of large amount of image data, a solution that FPGA extended SDRAM to store and buffer image data is presented.
主要介绍了用时序逻辑电路实现连续脉冲宽度测量的工作原理，并讨论了采用8031单片机的实现方案。
The principle of using sequential logic circuit and 8031 monolithic computer for realizing continuous pulse duration measure are introduced.
利用单片机IO口模拟I2C时序，实现了视频解码芯片控制；
To system needs, video decode program is designed by simulation of MCU's IO to I2C time sequence.
用程序实现状态机功能，有限状态机是指输出取决于过去输入部分和当前输入部分的时序逻辑电路。
Finite state machine is refers to the output depends on the past input part and the current input portion of temporal logic circuit.
单片机的P 1.1、P 1.2、P 1.3口分别接步进电机CBA绕组，他们按照一定的规律输出，各端口输出高低电平时序随电机正反转的要求不同而不同。
MCU P1.1, P1.2, P1.3, respectively, then I CBA stepper motor windings, according to the laws of their output, the output ports with high-low-level timing of the positive electric requirements vary.
单片机的P 1.1、P 1.2、P 1.3口分别接步进电机CBA绕组，他们按照一定的规律输出，各端口输出高低电平时序随电机正反转的要求不同而不同。
MCU P1.1, P1.2, P1.3, respectively, then I CBA stepper motor windings, according to the laws of their output, the output ports with high-low-level timing of the positive electric requirements vary.
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