输出读数据信号的数据时钟出的内存存储单元。
An output read-data signal clocks the data out of the memory storage cells.
同时产生同步、消隐、数据时钟等信号以及实现遥控、屏幕显示的控制功能。
The interface circuit also can produce synchronous, vanished and ensconced, digital clock signal and realize remote control, displaying on screen.
它提供一个数据时钟输出(DCO)用于在输出端捕获数据，以及一个帧时钟输出(FCO)用于发送新输出字节信号。
A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided.
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
实时时钟电路（X1228）被用作里程表，数据存储器和车速表中的警报。
A real-time clock circuit(X1228)is applied to be an hourmeter, data memorizer and alarm in speedometer.
数据库存储过程和触发器中的处理将使用数据库时钟。
Processing moved into stored procedures and triggers within the database will use the database clock.
有一个预定义的变量 total_time，它代表整个数据收集过程的时钟时间。
You have a pre-defined variable named total_time for the wall-clock time of the whole data collection.
有一个数据库、一台服务器和一个时钟。
尽管程序在应用服务器上运行，但是它将使用sql语句中的数据库时钟。
Even though the program runs on the application server, it will use the database clock in the SQL statement.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
第二天，当程序员用终端模拟窗口再次打开应用服务器和数据库服务器时，她向下看了一眼Windows任务栏中的时钟。
Later that day, when she had terminal emulation Windows opened against the application server and database server, the programmer looked down at the clock on the Windows taskbar.
数据和时钟线都是集电极开路的。
数据从主机发给从机可能会使用与从机发给主机相反的时钟沿。
Sending data from slave to master may use the opposite clock edge as master to slave.
另一个例子是设计从内部时钟获取数据的系统，用来取代请求用户输入。
Another example is designing a system that gets the date from the internal clock instead of asking for input from users.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
一些设备有两个时钟，一个用于“捕获”或者“显示”数据，另一个则用于提供将数据输入器件的时序。
Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
系统能够实现自动化灌溉，具有排水警示、实时时钟、历史数据查询、数据上传及双向通信等功能。
And, the system can realize functions of automatic irrigation, drainage warning, real time clock, historical data inquiry, data up-transmission and two-way communication.
在这种切换中，读出的数据有效前，数据总线至少需要有一个时钟的高阻状态。
The data bus must go into a high-impedance state at least one cycle before output of the latest data.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
着重阐述了软件设计中数据采集、显示、存储、时钟控制、RS485通信的编程思路。
It emphasized the programming thoughts of data collection, display, storage, clock control and RS485 communication in software design.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
只有当时钟线为低的时候，主机才可以改变数据线(也就是将数据写入到数据线)。数据将在时钟为高电平的时候被设备读龋。
The host changes the data line only when the Clock line is low, and data is read by the device when Clock is high.
对软磁盘的数据和时钟的同步和分离，只是锁相技术在计算机领域的应用之一。
The synchronization and separation of the data and clock from floppy disk driver are one of phase-lock techniques' use in computer field.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
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