该器件配置片内抽取滤波器，可获得最高性能和灵活性。
The on-chip decimation filter is configured for maximum performance and flexibility.
其中包括混频器模块、抽取滤波器模块、信号产生器模块。
The system includes mixer module, the abstracting filter module and the signal producing module.
数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
用户可以通过片上数字多路复用器访问各级抽取滤波器中的数据。
An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.
分析了级联积分梳状（CIC）滤波器的结构，证明其可以高效地胜任抽取滤波的任务。
The structure of Cascaded Integrator Comb (CIC) filter is discussed. CIC filter can efficiently perform the task of both decimating and filtering.
通过利用抽取滤波器的等价变换和多项分解性质，各滤波器级的硬件电路开销和运行功耗都得到了降低。
By utilizing equivalent transformation and polyphase decomposition of the decimation filter, both hardware cost and operating power of each sub-decimation filter were also reduced.
结合抽取滤波器的多项滤波结构，在一定条件下，推导出了一种含抽取正交解调接收机最优结构设计方法。
Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure.
根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
根据上述讨论的算法，本文设计了抽取滤波器组中CIC模块、HB模块和FIR模块的RTL实现结构。
By studying the algorithms of the filters, this dissertation works out RTL implementation architectures of the CIC module, HB module and FIR module.
该转换器采用了高阶MASH噪声成形技术，而其数字抽取滤波部分则由梳状滤波器与级联的半带滤波器构成。
The converter USES a high order MASH noise shaping technique and a digital decimation filtering part consisting of comb filters and cascade of half band filters.
最后的仿真表明：该设计方法使得CIC抽取滤波器性能得到改善，实现结构高效，在实际工程中有很大的应用价值。
Results from computer simulation suggested that the performance of modified CIC filters was improved and its architecture was efficient, which proved useful in engineering project.
对一些典型目标的傅氏系数作了数值计算，并用光学滤波把它们抽取出来。
The Fourier coefficients have been numerically calculated for the typical objects, and by using optical filtering the objects are extracted from pictures.
本文以实现整数倍抽取内插的CIC滤波器为基础，提出了一种实现分数倍采样率转换的时变CIC滤波结构。
This paper designs a time-variable CIC filter based on CIC filter for fractional ratio sample rate conversion.
然后介绍了数字化中频处理中的采样理论、正交混频解调、滤波抽取等基础理论。
The basic theory of IF signal processing, such as sample theory, quartered demodulating technology, filtering, draw-off and interpolating theory is discussed.
采用从HSL模型中抽取S值的方法实现图像灰度化处理，并通过中值滤波减少图像的噪声。
The S value from the HSL model was extracted to realize image grizzled processing, and the image noise through the medium filtering was reduced.
本文研究了窄带信号条件下，高倍抽取的数字下变频设计，重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。
This paper studies high decimation ratio of digital downconverter given narrow-band signal, and especially analyze mul? stage decimation algorithm based on CIC filter and HB filter.
CIC滤波器已经被证明是在高速抽取和插值系统中非常有效的单元。
CIC filter has proven to be a very effective cell in high-speed decimation and interpolation systems.
音调周期抽取，采用逆滤波和降低取样率的平均幅差函数方法。
Extraction of pitch period: An inverse filtered-simplified-AMDF method is proposed.
现研究了一种具有线性相位的最大抽取FIR余弦调制滤波器组，该滤波器组中每一个滤波器都具有线性相位，且由原型滤波器经余弦序列调制得到。
In this paper we study linear phase maximally decimated FIR cosine modulated filter banks, in which each filter has linear phase and is obtained by modulating the prototype filter by cosine sequences.
然后根据降速率信号处理的要求，给出了本文所使用的抽取方案以及具体的半带滤波器设计。
Then according to the request of down-speed signals processing, the extraction scheme and the detailed half band filter design are provided.
重点研究了抽取技术，并将这种技术应用于数字中频系统，设计了CIC滤波器和半带滤波器；
The emphasis of research is decimation technology. Design CIC filters and Halfband filters with this theroy.
研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器、级联补偿滤波器、级联根升余弦滤波器的多级抽样频率算法。
In this paper, the high decimation ratio of digital down converter is studied and the multi-stage decimation algorithm is especially analyzed based on CIC filter, CFIR filter and RRC filter.
将可编程抽取、插值器与多级积分梳状滤波器（CIC）相配合，实现高效数字抽取和插值模块。
A programmable decimation and interpolation ratio module onnected with multistage cascade integrator comb (CIC) filter is designed to implement high efficient decimator and interpolator.
剩余4倍抽取采用两级半带滤波器和升幅FIR实现。
The last 4 times decimation was achieved by two half band filters and a droop FIR.
用户对滤波器响应、滤波器系数和抽取率拥有完全的控制权。
The user has complete control over the filter response, the filter coefficients and the decimation ratio.
若信号不进行滤波就抽取，信号将出现混叠，那么其关键问题就是抽取前的滤波。
If the signals are sampled before the filtering, the signals' spectrum will be aliasing. The filtering technology is a key issue before the sampling.
波带滤波器和CIC滤波器的基础上设计了多级抽取系统。
Design multi-stage decimation system on the basis of Halfband filters and CIC filters.
介绍一种可用于语音处理的低功耗、高速率的抽取和内插数字滤波器的集成电路设计方法。
A low power, high speed design method of decimation and interpolation digital filters for audio signal processing is described.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
此外，该器件提供可编程抽取率，而且如果数字FIR滤波器的默认特征不适合应用要求，还可对其进行调整。
In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application.
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