多维并行级联码的译码普遍采用并行译码方法。
The parallel decoding method of a parallel concatenation of multiple codes is well known.
串行译码方法不仅计算简单，而且所达到的性能与并行译码方法相近。
Though it is simpler than the parallel decoding method in calculation, it gives the same performance as the parallel decoding method.
本译码器采用改进的最小和译码算法及符合CMMB标准要求的部分并行译码器结构。
The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
该文根据准循环ldpc码的结构特点，提出了一种同步部分并行结构的译码器。
Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
该结构采用译码的方式依次选通每个扫描小组，使得扫描小组中的存储元件并行地控制和观测。
Each scan group is selected in turn by decoder so that storage elements in each scan group can be controlled and observed in parallel.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
该算法适合于并行的译码结构，能够在保持译码性能不变的同时，加快译码速度。
The proposed algorithm is applicable to the parallel decoding structure and can improve the decoding speed meanwhile keeping the decoding performance unchanged.
利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。
According to the structure of Quasi-Cyclic LDPC code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture.
虽然HP - TBTC结构是以牺牲一定的硬件资源为代价换取编译码的并行处理，但它可以成倍地提高编译码处理速度。
HP-TBTC can be implemented in parallel to obtain much higher encoding and decoding speed at the cost of more hardware resource.
并行级联分组码也已经显示出接近香农理论极限的卓越性能，而其译码采用的也是一种相对简单的迭代译码技术。
The parallel concatenated block code has been shown to yield remarkable performance close to theoretical limits, yet admitting a relatively simple iterative decoding technique.
由于采用迭代译码算法，而且是并行算法，因此能提高译码速度，降低译码的复杂度。
As a result of using the iterative decoding algorithm, which is a parallel algorithm, it can improve the decoding speed and reduce the complexity of decoding.
由于采用迭代译码算法，而且是并行算法，因此能提高译码速度，降低译码的复杂度。
As a result of using the iterative decoding algorithm, which is a parallel algorithm, it can improve the decoding speed and reduce the complexity of decoding.
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